Many modern electronic circuits (e.g., microcontrollers) use internal CMOS oscillators to generate clocks. In many applications, a low variation CMOS oscillator is needed. Conventional CMOS oscillators are manually trimmed by test engineers with dedicated, external tester resources. Some CMOS oscillators use a resistive-capacitive (RC) structure.
A conventional RC oscillator with a Schmitt trigger is shown in FIG. 1A. The RC oscillator 100 includes a capacitor 102 (C), a Schmitt trigger 104 (11) and a resistor 106 (R). The output clock 108 has a frequency that is directly proportional to the RC product. A typical integrated poly-silicon resistor can provide a relative frequency variation of about +/−25% and a typical integrated CMOS capacitor can provide a relative frequency variation of about +/−15%. In this case, the overall relative frequency variation can have a +/−40% total frequency variation. Even using other RC oscillator topologies (e.g., charging and discharging an internal capacitor with controlled current, etc.) it is not easy to find a solution where the frequency does not directly depend on the RC product. Thus, the oscillator frequency directly depends on process distribution which can cause values for the resistor and capacitor to vary. One common technique for reducing RC oscillator variation is to use trimming bits to trim the resistor and/or the capacitor to compensate for process variation.
FIG. 1B illustrates a conventional RC oscillator 110 that uses trimming bits Dn, . . . , D0 to trim the resistor 106 using, for example, a binary-weighted resistive network. Depending on the digital code set on the resistive network, the oscillator frequency can be increased, decreased or maintained. In this example, the first digital code produces clock 112 (CodeA) and a second digital code produces code 114 (CodeB). FIG. 2 shows an example frequency variation F0-F4 obtained using digital codes 1-5.